Comparative analysis of adiabatic logic challenges for low power CMOS circuit designs

In a deep sub-micrometer regime as the scaling improves (reduction in feature size), gate oxide becomes thin and threshold voltage gets reduced, and thus the contribution in power dissipation due to leakage currents increases. Consequently, leakage currents in small feature size devices become a critical factor for low power applications. As the feature size has been reduced very much already, therefore it becomes very important to identify new techniques for power reduction instead of decreasing the feature size. Energy recovery technique is such a prominent technique which recycles the stored charge at different nodes and reduces power dissipation significantly. This paper reviews various energy recovery techniques based on different adiabatic logics. Analysis and comparison of different adiabatic logic techniques based on various parameters such as, the frequency of operation, gm technology used, supply voltage, the number of devices used has been done successfully in this paper. This paper explores various aspects of energy recovery logics.