Approximate processing for low-power digital filtering using variable canonic signed digit coefficients

被引：3
|
作者：
Kim, YW
Yang, YM
Yoo, JT
Kim, SW
机构：
[1] Korea Univ, Sch Elect Engn, Sungbuk Ku, Seoul 136701, South Korea
[2] Anyang Univ, Dept Elect Engn, Anyang Shi, Kyonggi Do, South Korea
来源：
ELECTRONICS LETTERS | 2000年 / 36卷 / 01期
关键词：
D O I：
10.1049/el:20000050
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An alternative approximate processing method which dynamically adjusts the precision of the canonic signed digit (CSD) coefficients is proposed. This proposed method employs a two-stage search for finding approximated values of CSD coefficients. Experimental results show that the number of additions is reduced to 29.4%, 11.8%, and 3.9% for each approximation level.
引用
收藏
页码：11 / 13
页数：3
相关论文
共 50 条
  • [1] Low-power digital filtering using approximate processing with variable canonic signed digit coefficients
    Kim, YW
    Yang, YM
    Yoo, JT
    Kim, SW
    ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL II: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY, 2000, : 337 - 340
  • [2] Low-power digital filtering using approximate processing
    Ludwig, JT
    Nawab, SH
    Chandrakasan, AP
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (03) : 395 - 400
  • [3] Genetic algorithms for the design of digital filters using canonic signed digit coefficients
    Williams, T
    Ahmadi, M
    Miller, WC
    2004 7TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING PROCEEDINGS, VOLS 1-3, 2004, : 9 - 12
  • [4] Using signed digit arithmetic for low-power multiplication
    Crookes, D.
    Jiang, M.
    ELECTRONICS LETTERS, 2007, 43 (11) : 613 - 614
  • [5] Low-Power Digital Signal Processing Using Approximate Adders
    Gupta, Vaibhav
    Mohapatra, Debabrata
    Raghunathan, Anand
    Roy, Kaushik
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2013, 32 (01) : 124 - 137
  • [6] A low-power digital filter for decimation and interpolation using approximate processing
    Pan, CJ
    1997 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - DIGEST OF TECHNICAL PAPERS, 1997, 40 : 102 - 103
  • [7] Binary canonic signed digit multiplier for high-speed digital signal processing
    Lo Iacono, D
    Ronchi, M
    2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS, 2004, : 205 - 208
  • [8] A programmable FIR filter using serial-in-time multiplication and canonic signed digit coefficients
    Kosunen, M
    Halonen, K
    ICECS 2000: 7TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS & SYSTEMS, VOLS I AND II, 2000, : 563 - 566
  • [9] Low-power digital filter implementations using ternary coefficients
    Hezar, R
    Madisetti, VK
    VLSI SIGNAL PROCESSING, IX, 1996, : 179 - 188
  • [10] Approximate Arithmetic for Low-Power Image Median Filtering
    Monajati, M.
    Fakhraie, S. M.
    Kabir, E.
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2015, 34 (10) : 3191 - 3219
12345