A 17GHz Programmable Frequency Divider for Space Applications in a 130 nm SiGe BiCMOS Technology

被引：0

作者：

Herzel, Frank ^{[1
]}

Borngraeber, Johannes ^{[1
]}

Ergintav, Arzu ^{[1
]}

Kucharski, Maciej ^{[1
]}

Kissinger, Dietmar ^{[1
,2
]}

机构：

[1] IHP, Technol Pk 25, D-15236 Frankfurt, Oder, Germany

[2] Tech Univ Berlin, D-10587 Berlin, Germany

来源：

2015 IEEE BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING (BCTM) | 2015年

关键词：

PHASE-NOISE; SYNTHESIZER; GHZ;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A programmable frequency divider for fractional-N frequency synthesizers is presented. The input frequency range is from DC to 17 GHz for divider ratios from 16 to 255. We show by analysis and time-domain simulations that the quantization noise folding in a fractional-N PLL can be reduced tremendously, if a prescaler between VCO and programmable divider can be avoided by using this high-speed divider. The programmable divider was manufactured in a 130nm SiGe BiCMOS technology. Robust operation is obtained from a supply voltage VCC=2.3-3.9V. The measured divider phase noise floor for a 100MHz output signal is as low as -156 dBc/Hz. The chip occupies 1.7 mm(2) including bondpads and draws 154mA from a 2.3V supply.

引用

页码：133 / 136

页数：4

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