Quasi-parallel multi-path detection architecture using floating-gate-MOS-based CDMA matched filters

A quasi-parallel matching architecture for CDMA matched filters has been proposed aiming at high-speed and flexible multipath detection. In the architecture, a drastic reduction in the hardware volume has been achieved as compared with the fully-parallel matching architecture in Ref [1], while preserving the equivalent performance. The feasibility of the chip implementation has been examined based on the experimental results obtained from the floating-gate-MOS matched filters fabricated in a 0.35-mum CMOS technology. As a result, the system is estimated to dissipate 31.0mW occupying 4mm(2) chip area for the 512-chip length correlation at a rate of 4.096Mchip/s and four samples/chip.