A 2T Dual Port Capacitor-Less DRAM

被引：2

作者：

Li, Hui ^{[1
]}

Lin, Yinyin ^{[1
]}

机构：

[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai 201203, Peoples R China

来源：

IEEE ELECTRON DEVICE LETTERS | 2014年 / 35卷 / 02期

关键词：

Capacitor-less DRAM; embedded memory; two-transistor (2T) cell; floating-body cell; bipolar read; MEMORY; CELL;

D O I：

10.1109/LED.2013.2292586

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel two-transistor (2T) dual port capacitor-less DRAM concept based on bulk floating body is demonstrated for the first time in this letter. The read operation can be performed without disturbance of refresh or write. A novel read method is proposed to improve device performance especially at high temperature. Experimental results show a refresh cycle time of 1.28 s, an initial memory window of 192.84 mu A/mu m, and an initial signal sensing margin of 112.75 mu A/mu m with +/- 5 sigma variations at 85 degrees C. The 2T cell is very promising for high-speed, low-power, and low-cost embedded DRAM application.

引用

页码：187 / 189

页数：3

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