A Multi-Phases Time-to-Digital Converter With a Differentiel Vernier Ring Oscillator

This paper reports the development of an adjustable, Time-to-Digital Converter (TDC) based on two vernier Ring Oscillators (RO). The TDC aims to measure timing in Resistive Plate Chamber (RPC) detector for CMS experiment. Considering previous designs, the contribution from power supply noise and intrinsic transistor noise had been minimize with differential stages and proper transistor sizing. In order to reduce the dead time inherent to Vernier TDC architecture, as many Phase Detector (PD) as possible had been implement. Such functionality permits to choose whether reducing the dead time or measuring redundantly the start-stop time difference for an improved resolution. The 81-PD Matrix is the originality of the design. Indeed, the information of the start-stop time is present at each inverter output with a predictable offset in term of time. The inverter architecture introduce a constant delay at each stage of the chain with a phase inversion. By recording the counter when a phase detection occurs at each inverter output permit to revert back to the start-stop time. The prototype TDC fabricated in a 130-nm technology consumes 8.5 mW power under 1.2-V supply. The measurement of this chip shown a timing accuracy of 5.48 ps at a timing resolution of 8 ps for the first data allowed by the first phase detection.