A run-time word-level reconfigurable coarse-grain functional unit for a VLIW processor

被引:0
|
作者
Busa, NG [1 ]
Sala, CR [1 ]
机构
[1] Philips Res Labs, NL-5656 AA Eindhoven, Netherlands
来源
ISSS'02: 15TH INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS | 2002年
关键词
reconfigurable logic; VLIW processors; architectural synthesis;
D O I
10.1109/ISSS.2002.1227150
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Nowadays, new DSP applications are offering combined and flexible multimedia and telecom services. VLIW processor architectures, which include dedicated but inflexible functional units, are usually tuned to a single specific application. In order to accelerate a wide range of applications, we propose a VLIW processor containing a novel run-time reconfigurable functional unit (RC-FU). Only a few hundred bits and few cycles are necessary to configure a new coarse-grain operation on the RC-FU unit. After reconfiguring its internal datapath and microprogram, the RC-FU can execute a number of look-alike DSP functions, such as 8-point DCT or 4-point FFT. The RC-FU itself is a VLIW processor and the configuration contexts are generated using a high-level synthesis tool. The proposed RC-FU provides high processing power and can be efficiently tuned to the requirements of a variety of DSP applications.
引用
收藏
页码:44 / 49
页数:6
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