Reduction of off-current in self-aligned double-gate TFT with mask-free symmetric LDD

被引：6
作者：
Zhang, SD [1 ]
Han, RQ
Sin, JKO
Chan, M
机构：
[1] Peking Univ, Inst Microelect, Beijing 100871, Peoples R China
[2] Hong Kong Univ Sci & Technol, Dept Elect & Elect Engn, Hong Kong, Peoples R China
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2002年 / 49卷 / 08期
关键词：
double-gate; lightly doped drain (LDD); self-aligned; thin-film transistor (TFT);
D O I：
10.1109/TED.2002.801232
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this brief, the lateral electric field distribution in the channel of a double-gate TFT is studied and compared with that of a conventional single-gate TFT. The double-gate TFT is predicted to suffer from a more severe anomalous off-current than the single-gate TFT. A smart double-gate TFT technology is proposed to decrease the off-current. The unique feature of the technology is the lithography independent formation of the self-aligned double-gate and the symmetric lightly doped drain (LDD) structures. With the LDD applied, the anomalous off-current of the fabricated double-gate TFT is reduced by three orders of magnitude from the range of 10(-9) A/mum to 10(-12) A/mum. The orVoff current ratio is increased by three orders of magnitude accordingly from around 104 to 10(7).
引用
收藏
页码：1490 / 1492
页数：3
相关论文
共 10 条
  • [1] Gate-overlapped lightly doped drain poly-Si thin-film transistors for large area AMLCD
    Choi, KY
    Lee, JW
    Han, MK
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1998, 45 (06) : 1272 - 1279
  • [2] ANOMALOUS LEAKAGE CURRENT IN LPCVD POLYSILICON MOSFETS
    FOSSUM, JG
    ORTIZCONDE, A
    SHICHIJO, H
    BANERJEE, SK
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (09) : 1878 - 1884
  • [3] Kink-free polycrystalline silicon double-gate elevated-channel thin-film transistors
    Kumar, A
    Sin, JKO
    Nguyen, CT
    Ko, PK
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1998, 45 (12) : 2514 - 2520
  • [4] A C-switch cell for low-voltage and high-density SRAM's
    Kuriyama, H
    Ishigaki, Y
    Fujii, Y
    Maegawa, S
    Maeda, S
    Miyamoto, S
    Tsutsumi, K
    Miyoshi, H
    Yasuoka, A
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1998, 45 (12) : 2483 - 2488
  • [5] POLYSILICON TFT CIRCUIT-DESIGN AND PERFORMANCE
    LEWIS, AG
    LEE, DD
    BRUCE, BH
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (12) : 1833 - 1842
  • [6] Electrical characteristics of new LDD poly-Si TFT structure tolerant to process misalignment
    Min, BH
    Kanicki, J
    [J]. IEEE ELECTRON DEVICE LETTERS, 1999, 20 (07) : 335 - 337
  • [7] LEAKAGE CURRENT CHARACTERISTICS OF OFFSET-GATE-STRUCTURE POLYCRYSTALLINE-SILICON MOSFETS
    SEKI, S
    KOGURE, O
    TSUJIYAMA, B
    [J]. IEEE ELECTRON DEVICE LETTERS, 1987, 8 (09) : 434 - 436
  • [8] Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel
    Wong, HSP
    Chan, KK
    Taur, Y
    [J]. INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, : 427 - 430
  • [9] A novel self-aligned double-gate TFT technology
    Zhang, SD
    Han, RQ
    Sin, JKO
    Chan, MS
    [J]. IEEE ELECTRON DEVICE LETTERS, 2001, 22 (11) : 530 - 532
  • [10] Ultra-thin elevated channel poly-Si TFT technology for fully-integrated AMLCD system on glass
    Zhang, SD
    Zhu, CX
    Sin, JKO
    Li, JN
    Mok, PKT
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2000, 47 (03) : 569 - 575
1