Four-phase power clock generator for adiabatic logic circuits

被引：18
|
作者：
Bargagli-Stoffi, A
Iannaccone, G
Di Pascoli, S
Amirante, E
Schmitt-Landsiedel, D
机构：
[1] Tech Univ Munich, Lst Tech Elek, D-80333 Munich, Germany
[2] Univ Pisa, Dipartimento Ingn Informaz, I-56122 Pisa, Italy
来源：
ELECTRONICS LETTERS | 2002年 / 38卷 / 14期
关键词：
D O I：
10.1049/el:20020523
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A circuit for a four-phase trapezoidal power clock generator for adiabatic logic circuits realised with a double-well 0.25 mum CMOS technology and external inductors is proposed. The circuit, at a frequency of 7 MHz which is within the optimum frequency range for adiabatic circuits realised with 0.25 mum CMOS technology, has a conversion efficiency higher than 80%, and is robust with respect to parameter variations.
引用
收藏
页码：689 / 690
页数：2
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