A PGAS Execution Model for Efficient Stencil Computation on Many-Core Processors

被引：0
|
作者：
Ikei, Mitsuru [1 ]
Sato, Mitsuhisa [2 ]
机构：
[1] Univ Tsukuba, Dept Comp Sci, Intel KK, Intel Architecture Technol Grp, Tokyo, Japan
[2] Univ Tsukuba, Dept Comp Sci, Tsukuba, Ibaraki, Japan
来源：
2014 14TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON CLUSTER, CLOUD AND GRID COMPUTING (CCGRID) | 2014年
关键词：
many integrated core; parallel; PGAS; stencil code;
D O I：
10.1109/CCGrid.2014.20
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A efficient PGAS execution model on many-core processor for stencil computation is proposed and implemented. We use XcalableMP as a base language and we modify its runtime well fit in many-core processors. The runtime uses processes for parallel execution and global arrays of the stencil codes are broken into blocked sub-arrays placed on shared memory. Using two stencil codes, Laplace and Himeno, we evaluated its performance. In the evaluation, we show (1) Blocking improves locality of memory access during computation therefore improves total CPU execution time. (2) Direct data access using shared memory can relieve communication burden of sub-array halo exchanges.
引用
收藏
页码：305 / 314
页数：10
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