Single event-induced error propagation through nominally-off transmission gates

被引:13
作者
Hutson, J. M.
Ramachandran, V.
Bhuva, B. L.
Zhu, X.
Schrimpf, R. D.
Amusan, O. A.
Massengill, L. M.
机构
[1] Vanderbilt Univ, Dept Elect Engn & Comp Sci, Nashville, TN 37235 USA
[2] Texas Instruments Inc, Dallas, TX 75243 USA
关键词
65 nm technology; radiation effects; single event effects; transmission gate;
D O I
10.1109/TNS.2006.885842
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A single event-induced false latching mechanism in 65-nm D-flip-flops is identified and attributed to transient propagation through nominally-off CMOS transmission gates. This is a circuit-level effect initialized by single event transient (SET) pulses that causes the hit node voltage to exceed the voltage supply rails. Smaller devices are more susceptible to this effect because of smaller nodal capacitances. Circuit simulations indicate that this effect increases the temporal window where a data bit is vulnerable to a node strike by a quarter clock cycle.
引用
收藏
页码:3558 / 3562
页数:5
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