Effect of Irrelevant Variables on Faulty Wafer Detection in Semiconductor Manufacturing

被引:8
作者
Kim, Dongil [1 ]
Kang, Seokho [2 ]
机构
[1] Chungnam Natl Univ, Dept Comp Sci & Engn, 99 Daehak Ro, Daejeon 34134, South Korea
[2] Sungkyunkwan Univ, Dept Syst Management Engn, 2066 Seobu Ro, Suwon 16419, South Korea
基金
新加坡国家研究基金会;
关键词
faulty wafer detection; semiconductor manufacturing; irrelevant variable; supervised learning; prediction model; FEATURE-SELECTION; VIRTUAL METROLOGY; OPTIMIZATION; PREDICTION; ALGORITHM; SYSTEM;
D O I
10.3390/en12132530
中图分类号
TE [石油、天然气工业]; TK [能源与动力工程];
学科分类号
0807 ; 0820 ;
摘要
Machine learning has been applied successfully for faulty wafer detection tasks in semiconductor manufacturing. For the tasks, prediction models are built with prior data to predict the quality of future wafers as a function of their precedent process parameters and measurements. In real-world problems, it is common for the data to have a portion of input variables that are irrelevant to the prediction of an output variable. The inclusion of many irrelevant variables negatively affects the performance of prediction models. Typically, prediction models learned by different learning algorithms exhibit different sensitivities with regard to irrelevant variables. Algorithms with low sensitivities are preferred as a first trial for building prediction models, whereas a variable selection procedure is necessarily considered for highly sensitive algorithms. In this study, we investigate the effect of irrelevant variables on three well-known representative learning algorithms that can be applied to both classification and regression tasks: artificial neural network, decision tree (DT), and k-nearest neighbors (k-NN). We analyze the characteristics of these learning algorithms in the presence of irrelevant variables with different model complexity settings. An empirical analysis is performed using real-world datasets collected from a semiconductor manufacturer to examine how the number of irrelevant variables affects the behavior of prediction models trained with different learning algorithms and model complexity settings. The results indicate that the prediction accuracy of k-NN is highly degraded, whereas DT demonstrates the highest robustness in the presence of many irrelevant variables. In addition, a higher model complexity of learning algorithms leads to a higher sensitivity to irrelevant variables.
引用
收藏
页数:11
相关论文
共 50 条
  • [1] Joint modeling of classification and regression for improving faulty wafer detection in semiconductor manufacturing
    Kang, Seokho
    JOURNAL OF INTELLIGENT MANUFACTURING, 2020, 31 (02) : 319 - 326
  • [2] Machine learning-based novelty detection for faulty wafer detection in semiconductor manufacturing
    Kim, Dongil
    Kang, Pilsung
    Cho, Sungzoon
    Lee, Hyoung-joo
    Doh, Seungyong
    EXPERT SYSTEMS WITH APPLICATIONS, 2012, 39 (04) : 4075 - 4083
  • [3] Joint modeling of classification and regression for improving faulty wafer detection in semiconductor manufacturing
    Seokho Kang
    Journal of Intelligent Manufacturing, 2020, 31 : 319 - 326
  • [4] Key Feature Identification for Monitoring Wafer-to-Wafer Variation in Semiconductor Manufacturing
    Fan, Shu-Kai S.
    Hsu, Chia-Yu
    Tsai, Du-Ming
    Chou, Mabel C.
    Jen, Chih-Hung
    Tsou, Jen-Hsuan
    IEEE TRANSACTIONS ON AUTOMATION SCIENCE AND ENGINEERING, 2022, 19 (03) : 1530 - 1541
  • [5] Improving wafer handling performance in semiconductor manufacturing
    Chen, Heping
    Cheng, Hongtai
    Mooring, Ben
    INDUSTRIAL ROBOT-AN INTERNATIONAL JOURNAL, 2013, 40 (05) : 425 - 432
  • [6] Hybrid Feature Selection for Wafer Acceptance Test Parameters in Semiconductor Manufacturing
    Xu, Hongwei
    Zhang, Jie
    Lv, Youlong
    Zheng, Peng
    IEEE ACCESS, 2020, 8 : 17320 - 17330
  • [7] Auto-Labeling for Pattern Recognition of Wafer Defect Maps in Semiconductor Manufacturing
    Fan S.-K.S.
    Chen P.-C.
    Jen C.-H.
    Sethanan K.
    Journal of Manufacturing Science and Engineering, 2024, 146 (07):
  • [8] A resource portfolio planning methodology for semiconductor wafer manufacturing
    Chou, YC
    You, RC
    INTERNATIONAL JOURNAL OF ADVANCED MANUFACTURING TECHNOLOGY, 2001, 18 (01) : 12 - 19
  • [9] Prediction of Wafer Map Categories Using Wafer Acceptance Test Parameters in Semiconductor Manufacturing
    Lim, Martin Ying Song
    Sharma, Anurag
    Chin, Cheng Siong
    Yip, Tommy Chun Ming
    Ong, Jonathan Yoong Seang
    ARTIFICIAL INTELLIGENCE APPLICATIONS AND INNOVATIONS, AIAI 2022, PART II, 2022, 647 : 136 - 144
  • [10] A fast ramp-up framework for wafer yield improvement in semiconductor manufacturing systems
    Xu, Hong-Wei
    Zhang, Qi-Hua
    Sun, Yan-Ning
    Chen, Qun-Long
    Qin, Wei
    Lv, You-Long
    Zhang, Jie
    JOURNAL OF MANUFACTURING SYSTEMS, 2024, 76 : 222 - 233