Low power high speed I/O interfaces in 0.18μm CMOS

被引：0

作者：

Yan, Y ^{[1
]}

Szymanski, TH ^{[1
]}

机构：

[1] McMaster Univ, Opt Network Res Grp, Hamilton, ON L8S 3K1, Canada

来源：

ICECS 2003: PROCEEDINGS OF THE 2003 10TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3 | 2003年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The design and implementation of a low power high speed differential signaling input/output (I/O) interface in 0.18um CMOS technology is presented. The motivations for smaller signal swings in transmission are discussed. The prototype chip supports 4 Gbps data rate with less than 10mA current at 1.8V supply according to Cadence Spectre post-layout simulations. Performance comparisons between the proposed device and other signaling technologies reported recently are given.

引用

页码：826 / 829

页数：4

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