An Area-Efficient and High Throughput Hardware Implementation of Exponent Function

被引：2
作者：
Hussain, Muhammad Awais [1 ]
Lin, Shung-Wei [1 ]
Tsai, Tsung-Han [1 ]
机构：
[1] Natl Cent Univ, Dept Elect Engn, Taoyuan, Taiwan
来源：
2022 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 22) | 2022年
关键词：
Exponent function; VLSI; FPGA; Digital design; Hardware accelerator;
D O I：
10.1109/ISCAS48785.2022.9937238
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, an area-efficient and high throughput hardware implementation of the exponent function has been proposed. The proposed exponent calculation method eliminates the memory requirements leading to power and area savings. The pipelined hardware implementation results in a high-frequency design with reduced resources usage. The hardware implementation has been performed for Xilinx Virtex-4 FPGA board and TSMC 90nm process node. The throughput of 411.3 Mbps at 115.7 MHz frequency and 711.11 Mbps at 200 MHz frequency can be achieved for FPGA and ASIC design, respectively. The power consumption is 242mW and 6.1 mW for FPGA and ASIC platforms, respectively.
引用
收藏
页码：3369 / 3372
页数：4
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