An Area-Efficient and High Throughput Hardware Implementation of Exponent Function

In this paper, an area-efficient and high throughput hardware implementation of the exponent function has been proposed. The proposed exponent calculation method eliminates the memory requirements leading to power and area savings. The pipelined hardware implementation results in a high-frequency design with reduced resources usage. The hardware implementation has been performed for Xilinx Virtex-4 FPGA board and TSMC 90nm process node. The throughput of 411.3 Mbps at 115.7 MHz frequency and 711.11 Mbps at 200 MHz frequency can be achieved for FPGA and ASIC design, respectively. The power consumption is 242mW and 6.1 mW for FPGA and ASIC platforms, respectively.