A low-jitter phase-locked loop with a discriminator-aided edge detector

被引：0

作者：

Lu, Chih-Wen ^{[1
]}

Leong, Man Fai ^{[1
]}

机构：

[1] Natl Chi Nan Univ, Dept Elect Engn, Puli, Taiwan

来源：

PROCEEDINGS OF THE 6TH INTERNATIONAL CARIBBEAN CONFERENCE ON DEVICES, CIRCUITS, AND SYSTEMS | 2006年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

AA phase-locked loop (PLL), in which the ripple in the control voltage is suppressed to minimize the output phase jitter, is proposed. A discriminator-aided edge detector is added in the PLL to switch the outputs of the loop filter to reduce the ripple. The proposed PLL and the conventional circuit have been implemented in a 0.35-mu m CMOS process. Compared with the conventional PLL, the rms jitter is reduced from 19.0 ps to 18.3 ps and the peak-to-peak jitter is reduced from 148.2 ps to 139.1 ps.

引用

页码：315 / +

页数：2

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