A 90nm high volume manufacturing logic technology featuring Cu metallization and CDO low k ILD interconnects on 300 mm wafers

被引：21

作者：

Jan, CH ^{[1
]}

Anand, N ^{[1
]}

Allen, C ^{[1
]}

Bielefeld, J ^{[1
]}

Buehler, M ^{[1
]}

Chikamane, V ^{[1
]}

Fischer, K ^{[1
]}

Jain, A ^{[1
]}

Jeong, J ^{[1
]}

Klopcic, S ^{[1
]}

Marieb, T ^{[1
]}

Miner, B ^{[1
]}

Nguyen, P ^{[1
]}

Schmitz, A ^{[1
]}

Nashner, M ^{[1
]}

Scherban, T ^{[1
]}

Schroeder, B ^{[1
]}

Ward, C ^{[1
]}

Wu, R ^{[1
]}

Zawadzki, K ^{[1
]}

Thompson, S ^{[1
]}

Bohr, M ^{[1
]}

机构：

[1] Intel Corp, Hillsboro, OR USA

来源：

PROCEEDINGS OF THE IEEE 2004 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2004年

关键词：

D O I：

10.1109/IITC.2004.1345747

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A leading edge 90 nm, 300 mm wafer size interconnect technology featuring Cu, CDO low k ILD and industry's most aggressive 220 nm minimum metal pitch is being ramped into production for high performance Pentium(R) microprocessors, the first in industry, to our knowledge. Key enabling features for yield and reliability improvement to resolve challenges from weak thermo-mechanical properties of low k ILD and tight metal pitches for a production worthy interconnect process are presented.

引用

页码：205 / 207

页数：3

共 2 条

[1] 90 nm generation, 300mm wafer low k ILD/Cu interconnect technology
Jan, CH
Bielefeld, J
Buehler, M
Chikamane, V
Fischer, K
Hepburn, T
Jain, A
Jeong, J
Kielty, T
Kook, S
Marieb, T
Miner, B
Nguyen, P
Schmitz, A
Nashner, M
Scherban, T
Schroeder, B
Wang, PH
Wu, R
Xu, J
Zawadzki, K
Thompson, S
Bohr, M
[J]. PROCEEDINGS OF THE IEEE 2003 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2003, : 15 - 17
[2] Thompson S, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P61, DOI 10.1109/IEDM.2002.1175779

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