Gate failures effectively shape multiplexing

被引：12

作者：

Beiu, V. ^{[1
]}

Ibrahim, W. ^{[1
]}

Alkhawwar, Y. A. ^{[1
]}

Sulieman, M. H. ^{[1
]}

机构：

[1] United Arab Emirates Univ, Al Ain, U Arab Emirates

来源：

21ST IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT-TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS | 2006年

关键词：

D O I：

10.1109/DFT.2006.33

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper investigates the behavior of multiplexing (MUX) schemes in combination with the elementary gates. The two schemes under investigation are majority (MAJ) and NAND MUX The simulation results presented here are for single-electron technology but could easily be extended to CMOS. The components of the gates have been subjected only to geometric variations. Firstly, the gates and the two MUX schemes are analyzed theoretically. Secondly, simulations using probability transfer matrices (PTM) allow evaluating both MUX schemes at a redundancy factor R=6 Finally, the gates are compared in terms of their intrinsic probability of failure (with respect to geometric variations), and the two MUX schemes are weighted against the reliability enhancements they are bringing into the system. By comparing the simulation results from PTM with the ones based on (geometric) variations, this study gives deeper insights into the behavior of MUX schemes, and show that the gates play a major role, strongly affecting MUX systems.

引用

页码：29 / +

页数：2

共 24 条

[1]

[Anonymous], 2003, P INT WORKSHOP LOGIC

[2]

Beiu V, 2004, 2004 4TH IEEE CONFERENCE ON NANOTECHNOLOGY, P628

[3] Trends and challenges in VLSI circuit reliability [J].