High-speed I/O Buffer Modeling for Signal-integrity-based Design of VLSI Interconnects

Digital I/O buffers play an important role for the signal integrity (SI) simulation and timing analysis of high-speed VLSI interconnect networks, which often require the consideration of electromagnetic (EM) effects. In this paper, we give an overview of the recent advances in efficient macromodeling of nonlinear digital I/O buffers, including equivalent-circuit-based and neural-network-based approaches. The detailed equivalent circuit models axe accurate but computationally slow. On the other hand, the simplified equivalent circuit models are fast but only provide limited accuracy. The neural-network-based models axe good alternatives to those equivalent-circuit-based models, maintaining a good overall performance in terms of accuracy and speed. We demonstrate the neural-network-based approaches through an example of modeling a commercial high-speed integrated circuit (IC) device and its application to the SI simulation of high-speed interconnect networks.