Design of high-order phase-lock loops

被引：16
作者：
Carlosena, Alfonso
Manuel-Lazaro, Antonio
机构：
[1] Univ Publ Navarra, Dpt Elect & Elect Engn, E-31006 Pamplona, Spain
[2] Univ Politecn Cataluna, Ctr Tecnol Vilanova Geltru, Barcelona 08800, Spain
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2007年 / 54卷 / 01期
关键词：
analog signal processing; feedback systems; loop filters (LFs); phase-locked loops (PLLs);
D O I：
10.1109/TCSII.2006.883205
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The analysis, and design of third-order, (and higher) phase-locked loops (PLL) is difficult. This paper presents a novel approach to overcome these difficulties by allowing. high-order loops to be viewed as a natural extension of lower order ones. This is accomplished by adding nested first-order feedback loops around a basic first-order loop filter. Our approach will also be related to the concept of PLLs with aided acquisition. The model presented has been implemented and tested in Simulink.
引用
收藏
页码：9 / 13
页数：5
相关论文
共 10 条
[1]   LYAPUNOV REDESIGN OF ANALOG PHASE-LOCK LOOPS [J].
ABRAMOVITCH, DY .
IEEE TRANSACTIONS ON COMMUNICATIONS, 1990, 38 (12) :2197-2201
[2]   A fully integrated CMOS DCS-1800 frequency synthesizer [J].
Craninckx, J ;
Steyaert, MSJ .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (12) :2054-2065
[3]  
Egan WilliamF., 1998, PHASE LOCK BASICS
[4]  
Gardner FM, 2005, PHASELOCK TECHNIQUES, 3RD EDITION, P1, DOI 10.1002/0471732699
[5]   Analysis of charge-pump phase-locked loops [J].
Hanumolu, PK ;
Brownlee, M ;
Mayaram, K ;
Moon, UK .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2004, 51 (09) :1665-1674
[6]   Phase-locked loop design for on-chip tuning applications [J].
Osa, JI ;
Carlosena, A ;
Lopez-Martin, AJ .
ELECTRONICS LETTERS, 2000, 36 (08) :699-701
[7]  
PREZEDPELSKI AB, 1979, ELECT DESIGN, V16
[8]  
RAZAVI B, 1996, TUTORIAL MONOLITHIC
[9]   Phase-domain all-digital phase-locked loop [J].
Staszewski, RB ;
Balsara, PT .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2005, 52 (03) :159-163
[10]  
STEPHENS DR, 1998, PHASE LOCK LOOPS WIR
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