Hardware optimization and serial implementation of a novel spiking neuron model for the POEtic tissue

被引：6

作者：

Torres, O

Eriksson, J

Moreno, JM

Villa, A

机构：

[1] Tech Univ Catalunya, ES-08034 Barcelona, Spain

[2] Univ Lausanne, Lab Neuroheurist, CH-1005 Lausanne, Switzerland

[3] Univ Grenoble 1, INSERM, U318, CHUG Michallon,Lab Neurobiophys, F-38043 Grenoble, France

来源：

BIOSYSTEMS | 2004年 / 76卷 / 1-3期

关键词：

spiking neuron; STDP; hardware; serial implementation;

D O I：

10.1016/j.biosystems.2004.05.012

中图分类号：

Q [生物科学];

学科分类号：

07 ; 0710 ; 09 ;

摘要：

In this paper we describe the hardware implementation of a spiking neuron model, which uses a spike time dependent plasticity (STDP) rule that allows synaptic changes by discrete time steps. For this purpose an integrate-and-fire neuron is used with recurrent local connections. The connectivity of this model has been set to 24 neighbours, so there is a high degree of parallelism. After obtaining good results with the hardware implementation of the model, we proceed to simplify this hardware description, trying to keep the same behaviour. Some experiments using dynamic grading patterns have been used in order to test the learning capabilities of the model. Finally, the serial implementation has been realized. (C) 2004 Elsevier Ireland Ltd. All rights reserved.

引用

页码：201 / 208

页数：8

共 6 条

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[4] A New Hardware-oriented Spiking Neuron Model Based on SET and Its Properties
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[5] A novel approach for the implementation of large scale spiking neural networks on FPGA hardware
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