Design and Optimization of the NAND ESD Clamp in CMOS Technology

被引：6
作者：
Liu, Jian [1 ]
Peachey, Nathaniel [1 ]
机构：
[1] Qorvo Inc, ESD Engn, Greensboro, NC 27409 USA
来源：
2019 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2019年
关键词：
Electrostatic Discharge (ESD); Tunable Triggering Voltage (V-t1); RC-Based Power-Rail Clamp; Human Body Model (HBM); Transmission Line Pulse (TLP);
D O I：
10.1109/irps.2019.8720605
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper introduces an RC-based power-rail ESD clamp circuit which is controlled by a NAND-based latching trigger circuit. It remains off during circuit power up and normal operation but turns on rapidly in an ESD transient event. The clamp has a tunable triggering voltage to enable design flexibility.
引用
收藏
页数：4
相关论文
共 12 条
[1]   Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test [J].
Ker, Ming-Dou ;
Yen, Cheng-Cheng .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (11) :2533-2545
[2]  
Li J., 2004, P EOS ESD S, P273
[3]  
MERRILL R, 1993, ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM 1993, P233
[4]  
Miller J. W., 1999, US Patent, Patent No. 5946177
[5]  
Peachey N., 2018, US Patent, Patent No. [9972999B2, 9972999]
[6]  
Peachey N., 2011, US Patent, Patent No. [7929263B1, 7929263]
[7]   A new flip-flop-based transient power supply clamp for ESD protection [J].
Sarbishaei, Hossein ;
Semenov, Oleg ;
Sachdev, Manoj .
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2008, 8 (02) :358-367
[8]  
Smith J., 2003, P EOS ESD S, P8
[9]  
Stockinger M., 2003, PROC EOSESD S, P17
[10]   Active ESD shunt with transistor feedback to reduce latchup susceptibility or false triggering [J].
Tong, PCF ;
Chen, WS ;
Jiang, RHC ;
Hui, J ;
Xu, PP ;
Liu, PZQ .
IPFA 2004: PROCEEDINGS OF THE 11TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS, 2004, :89-92
12