Parallel, asynchronous, fuzzy logic systems realized in CMOS technology

Fuzzy systems play an important role in many industrial applications. Depending on the application, they can be implemented using different techniques and technologies. Software implementations are the most popular, which results from the ease of such implementations. This approach facilitates modifications and testing. On the other hand, such realizations are usually not convenient when high data rate, low cost per unit, and large miniaturization are required. For this reason, we propose efficient, fully digital, parallel, and asynchronous (clock-less) fuzzy logic (FL) systems suitable for the implementation as ultra low-power-specific integrated circuits (ASICs). On the basis of our former work, in which single FL operators were proposed, here we demonstrate how to build larger structures, composed of many operators of this type. As an example, we consider Lukasiewicz neural networks (LNN) that are fully composed of selected FL operators. In this work, we propose FL OR, and AND Lukasiewicz neurons, which are based on bounded sum and bounded product FL operators. In the comparison with former analog implementations of such LNNs, digital realization, presented in this work, offers important advantages. The neurons have been designed in the CMOS 130nm technology and thoroughly verified by means of the corner analysis in the HSpice environment. The only observed influence of particular combinations on the process, voltage, and temperature parameters was on delays and power dissipation, while from the logical point of view, the system always worked properly. This shows that even larger FL systems may be implemented in this way.