A Low-Power Integrated Circuit for Interaural Time Delay Estimation Without Delay Lines

被引：4
|
作者：
Chacon-Rodriguez, A. [1 ]
Martin-Pirchio, F. [2 ,3 ]
Sanudo, S. [2 ,3 ]
Julian, P. [2 ,3 ]
机构：
[1] Univ Nacl Mar del Plata, Lab Componentes Elect, RA-7600 Mar Del Plata, Argentina
[2] Univ Nacl Sur, DIEC, RA-8000 Bahia Blanca, Buenos Aires, Argentina
[3] Univ Nacl Sur, CONICET, IIIE, RA-8000 Bahia Blanca, Buenos Aires, Argentina
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2009年 / 56卷 / 07期
关键词：
Acoustic signal processing; bearing angle estimation; CMOS digital integrated circuits; correlation-derivative circuit; delay estimation correlation methods; direction of arrival estimation; low-power consumption; low-power sensor networks; microphone arrays; LOCALIZER;
D O I：
10.1109/TCSII.2009.2023281
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A low-power IC for the estimation of the delay between two infinitely clipped (digital) signals is designed and implemented in a 0.35-mu m standard CMOS technology. The proposed circuit is based on a sliding-mode control system and does not need past values of the inputs, which are usually stored using chains of digital registers or analog delay lines and significantly increase the power consumption. The IC is intended to work in ultralow-power miniature sensor network nodes performing localization in the audio range [20, 1000] Hz, as part of a forest environmental protection network. Power dissipation results show a core power consumption of 1.04 mu W at 3.3 V and only 282 nW at 1.8 V-in both cases with a clock frequency of 200 kHz. The circuit is fully operative and was successfully tested on field as part of a low-power bearing sensor unit.
引用
收藏
页码：575 / 579
页数：5
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