Reversible logic-based image steganography using quantum dot cellular automata for secure nanocommunication

被引:46
作者
Debnath, Bikash [1 ]
Das, Jadav Chandra [1 ]
De, Debashis [1 ]
机构
[1] West Bengal Univ Technol, Dept Comp Sci & Engn, BF 142,Sect 1, Kolkata 700064, W Bengal, India
关键词
quantum dots; cellular automata; steganography; quantum gates; image coding; decoding; telecommunication security; CMOS logic circuits; integrated circuit reliability; reversible logic-based image steganography; quantum dot cellular automata; nanocommunication security; Feynman gate; reversible encoder; reversible decoder; nanocommunication circuit; quantum cost; complementary metal-oxide-semiconductor circuit; image steganography LSB technique; signal-to-noise ratio; SNR; mean squared error; MSE; QCA encoder-decoder circuit; reversible computing; heat energy dissipation; single missing-additional cell-based defect analysis; circuit reliability; QCADesigner tool; Matlab; cost effectiveness functionality; DESIGN; QCA; CIRCUITS; BINARY; ADDER;
D O I
10.1049/iet-cds.2015.0245
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This study introduces a novel architecture for image steganography using reversible logic based on quantum dot cellular automata (QCA). Feynman gate is used to achieve the reversible encoder and decoder for image steganography. A Nanocommunication circuit for image steganography is shown using proposed encoder/decoder circuit. The proposed QCA circuits have lower quantum cost than traditional designs. It shows the cost effectiveness functionality of the proposed designs. The proposed circuit has 28.33% improvement in terms of area over complementary metal-oxide-semiconductor circuit. To perform image steganography LSB technique is used; signal-to-noise ratio (SNR), peak SNR and mean squared error (MSE) are also computed. The proposed QCA encoder/decoder circuit is suitable for reversible computing. To establish this, the heat energy dissipation by the proposed encoder/decoder circuit is estimated. The estimation shows that the encoder/decoder circuit has very low energy dissipation. Single missing/additional cell-based defect analysis is also explored in this study. Reliability of the circuit is tested against different temperatures. Implementation and testing of the circuit are achieved using QCADesigner tool. MATLAB is used to produce the input to the proposed circuit.
引用
收藏
页码:58 / 67
页数:10
相关论文
共 28 条
  • [1] High frequency CMOS amplifier with improved linearity
    Ali, M. Tanseer
    Wu, Ruiheng
    Mao, Luhong
    Callaghan, Peter
    Rapajic, Predrag
    [J]. IET CIRCUITS DEVICES & SYSTEMS, 2014, 8 (06) : 450 - 458
  • [2] A novel 7 Gbps low-power CMOS ultra-wideband pulse generator
    Arafat, M. A.
    Harun-ur-Rashid, A. B. M.
    [J]. IET CIRCUITS DEVICES & SYSTEMS, 2012, 6 (06) : 406 - 412
  • [3] Coplanar wire crossing in quantum cellular automata using a ternary cell
    Arjmand, Mohsen M.
    Soryani, Mohsen
    Navi, Keivan
    [J]. IET CIRCUITS DEVICES & SYSTEMS, 2013, 7 (05) : 263 - 272
  • [4] Boneh D, 2011, LECT NOTES COMPUT SC, V6597, P253, DOI 10.1007/978-3-642-19571-6_16
  • [5] Adder designs and analyses for quantum-dot cellular automata
    Cho, Heumpil
    Swartzlander, Earl E., Jr.
    [J]. IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2007, 6 (03) : 374 - 383
  • [6] Node duplication and routing algorithms for quantum-dot cellular automata circuits
    Chung, W. J.
    Smith, B.
    Lim, S. K.
    [J]. IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2006, 153 (05): : 497 - 505
  • [7] Das J. C., 2015, QUANT MATTER, V4, P504, DOI DOI 10.1166/QM.2015.1225
  • [8] Das J. C., 2012, P INT C RADD COMM CO, P343, DOI [10.1109/ICRCC.2012.6450583, DOI 10.1109/ICRCC.2012.6450583]
  • [9] Novel low power reversible binary incrementer design using quantum-dot cellular automata
    Das, Jadav Chandra
    De, Debashis
    [J]. MICROPROCESSORS AND MICROSYSTEMS, 2016, 42 : 10 - 23
  • [10] Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication
    Das, Jadav Chandra
    De, Debashis
    [J]. FRONTIERS OF INFORMATION TECHNOLOGY & ELECTRONIC ENGINEERING, 2016, 17 (03) : 224 - 236