SRAM circuit with expanded operating margin and reduced stand-by leakage current using thin-BOX FD-SOI transistors

被引：7

作者：

Yamaoka, Masanao ^{[1
]}

Tsuchiya, Ryuta ^{[1
]}

Kawahara, Takayuki ^{[1
]}

机构：

[1] Hitachi Ltd, Cent Res Lab, Kokubunji, Tokyo, Japan

来源：

2005 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS | 2005年

关键词：

D O I：

10.1109/ASSCC.2005.251677

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We propose a low-power SRAM circuit using thin-BOX FD-SOI transistors. The SRAM circuit uses back-gate bias effectively, and acquires high operating margin and high speed operation under low supply voltage. The leakage current in standby state is reduced. This SRAM achieves 30% faster writing time under low-voltage operation, and 90% less stand-by power.

引用

页码：109 / 112

页数：4

共 5 条

[1]

SEEVINCK E, 1987, JSSC, V22, P747

[2] Silicon on thin BOX: A new paradigm of the CMOSFET for low-power and high-performance application featuring wide-range back-bias control [J].

Tsuchiya, R ;

Horiuchi, M ;

Kimura, S ;

Yamaoka, M ;

Kawahara, I ;

Maegawa, S ;

Ipposhi, T ;

Ohji, Y ;

Matsuoka, H .

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, :631-634

[3] Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology [J].

Yamaoka, M ;

Osada, K ;

Tsuchiya, R ;

Horiuchi, M ;

Kimura, S ;

Kawahara, T .

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2004, :288-291

[4] A 300MHz 25μA/Mb leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor [J].

Yamaoka, M ;

Shinozaki, Y ;

Maeda, N ;

Shimazaki, Y ;

Kato, K ;

Shimada, S ;

Yanagisawa, K ;

Osada, K .

2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, 2004, 47 :494-495

[5]

YAMAOKA M, 2005, ISSCC, P480

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