IAPDL-based low-power adiabatic programmable logic array

被引：1

作者：

Lau, KT ^{[1
]}

Liu, F ^{[1
]}

机构：

[1] Nanyang Technol Univ, Ctr Microelect, Sch Elect & Elect Engn, Singapore 639798, Singapore

来源：

MICROELECTRONICS JOURNAL | 2000年 / 31卷 / 04期

关键词：

adiabatic pseudo-domino logic; programmable logic array; HSPICE;

D O I：

10.1016/S0026-2692(99)00105-6

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel low power programmable logic array structure based on adiabatic switching is presented. Simulation results using HSPICE with 0.8 mu m technology designs show that the power savings of the proposed adiabatic programmable logic array (PLA) circuit is up to 60%, compared to the dynamic PLA circuit. Compared to APDL (Adiabatic Pseudo-Domino Logic) PLA, the power saving is about 15% and the device count savings is about 20%. The power saving is improved further at lower supply voltages. At 2 V Vdd and 200 MHz clock frequency, the power saving is about 25% compared to APDL PLA. Compared to static PLA, the power saving is even more significant. HSPICE simulations also show that the proposed PLA can function correctly up to I GHz at 5 V Vdd, and the supply voltage can be scaled down to 2 V at 200 MHz. (C) 2000 Elsevier Science Ltd. All rights reserved.

引用

页码：235 / 238

页数：4

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