IAPDL-based low-power adiabatic programmable logic array

A novel low power programmable logic array structure based on adiabatic switching is presented. Simulation results using HSPICE with 0.8 mu m technology designs show that the power savings of the proposed adiabatic programmable logic array (PLA) circuit is up to 60%, compared to the dynamic PLA circuit. Compared to APDL (Adiabatic Pseudo-Domino Logic) PLA, the power saving is about 15% and the device count savings is about 20%. The power saving is improved further at lower supply voltages. At 2 V Vdd and 200 MHz clock frequency, the power saving is about 25% compared to APDL PLA. Compared to static PLA, the power saving is even more significant. HSPICE simulations also show that the proposed PLA can function correctly up to I GHz at 5 V Vdd, and the supply voltage can be scaled down to 2 V at 200 MHz. (C) 2000 Elsevier Science Ltd. All rights reserved.