Variation-Aware Routing For FPGAs

被引：0

作者：

Sivaswamy, Satish ^{[1
]}

Bazargan, Kia ^{[1
]}

机构：

[1] Univ Minnesota, Dept Elect Engn, Minneapolis, MN 55455 USA

来源：

FPGA 2007: FIFTEENTH ACM/SIGDA INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE GATE ARRAYS | 2007年

关键词：

Statistical Timing Analysis; FPGA Routing;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the effects of variations. The FPGA community on the other hand, has only recently started focussing on the effects of variations. This paper presents a comparative study of the impact of variations on designs mapped to FPGAs and ASICs to get a measure of the severity of the problem in both the FPGA and ASIC domains. We also propose a variation aware router that reduces the yield loss by 7.61X, or the circuit delay by 3.95% for the same yield for the MCNC benchmarks.

引用

页码：71 / 79

页数：9

共 17 条

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