Compact realization of phase-locked loop using digital control

This paper describes a phase-locked loop (PLL) with digital control featuring a binary quantizing circuit, a synchronizing algorithm, a lock detector and a compact D/A converter. The binary quantizing circuit and synchronizing algorithm make it possible to compare phase and frequency together and to reduce digital control logic by half. Interpolation of upper-bit D/A converter output by lower-bit output reduces the number of current sources of a 9 bit D/A converter from 511 to 80. SPICE simulation with a 0.25 mu m CMOS has demonstrated that the development of 200 MHz PLL using digital control is feasible.