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- [1] Effect of Microstructure on Via Extrusion Profile and Reliability Implication for Copper Through-Silicon Vias (TSVs) Structures 2014 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE / ADVANCED METALLIZATION CONFERENCE (IITC/AMC), 2014, : 377 - 379
- [2] Effects of Etch Rate on Scallop of Through-Silicon Vias (TSVs) in 200mm and 300mm Wafers 2011 IEEE 61ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2011, : 1130 - 1135
- [4] Investigate the Microstructure Changes in Cu Through-Silicon Vias (TSVs) under Thermal Process 2012 13TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING (ICEPT-HDP 2012), 2012, : 397 - 399
- [6] Susceptibility Evaluation of 3D Integrated Static Random Access Memory with Through-Silicon Vias (TSVs) 17TH IEEE INTERNATIONAL CONFERENCE ON IC DESIGN AND TECHNOLOGY (ICICDT 2019), 2019,
- [10] Microstructure Evolution and Defect Formation in Cu Through-Silicon Vias (TSVs) During Thermal Annealing Journal of Electronic Materials, 2012, 41 : 712 - 719