Computational modeling of vortex shedding in water cooling of 3D integrated electronics

This work aims at understanding the flow and heat transfer through a microcavity populated with micropins, representing a layer of a 3D integrated electronic chip stack with integrated cooling. The resulting vortex shedding behavior and its effect on the heat removal is analyzed in the Reynolds number (Re) range from 60 to 450. The lateral confinement, expressed as the ratio of diameter to lateral distance between two cylinders' centers, is varied between 0.1 and 0.5; the longitudinal confinement (diameter to longitudinal distance between two cylinders' centers) between 0.25 and 0.5; and vertical confinement (diameter to microcavity height ratio) between 0.1 and 0.5. For a single pin, as the lateral confinement is increased, the Strouhal number (St) and the shedding frequency increase by up to 100%. The thermal performance represented by the spatiotemporal averaged Nusselt number (Nu), based on the average pin surface and fluid temperatures, is also enhanced by over 30%. A direct relationship between Nu and the shedding frequency was found. For a row of pins, Nu in the vortex shedding regime was found to be up to 300% higher compared to the steady case. A decrease in the longitudinal confinement, tested with rows of pins (either with 50 or 25 pins) in the streamwise direction, led to an upstream migration of the vortex shedding location and in more homogeneous but higher wall temperatures. This coincided with a drastic reduction of pressure losses and a 30% Nu enhancement for the same pumping power. Finally, the vertical confinement is also investigated with 3D simulations around a single cylinder. With increasing Re and vertical confinement, the wake becomes strongly three-dimensional. For a given Re, the increase of vertical confinement naturally shows a suppression or even a complete elimination of the vortex shedding due to a strong end-wall effect. Our results shed light on the effects of confinement on vortex shedding and related heat transfer in the integrated cooling of 3D chip stacks. (C) 2013 Elsevier Inc. All rights reserved.