Height-selective etching for regrowth of self-aligned contacts using MBE

被引：10

作者：

Burek, G. J. ^{[1
,2
]}

Wistey, M. A. ^{[1
,2
]}

Singisetti, U. ^{[1
,2
]}

Nelson, A. ^{[3
]}

Thibeault, J. ^{[1
,2
]}

Bank, S. R. ^{[4
]}

Rodwell, M. J. W. ^{[1
,2
]}

Gossard, A. C. ^{[1
,2
]}

机构：

[1] Univ Calif Santa Barbara, ECE Dept, Santa Barbara, CA 93106 USA

[2] Univ Calif Santa Barbara, Dept Mat, Santa Barbara, CA 93106 USA

[3] Univ St Thomas, St Paul, MN 55105 USA

[4] Univ Texas Austin, ECE Dept, Austin, TX 78712 USA

来源：

JOURNAL OF CRYSTAL GROWTH | 2009年 / 311卷 / 07期

基金：

美国国家科学基金会;

关键词：

Etching; Nanostructures; Molecular beam epitaxy; Selective deposition; Semiconducting III-V materials; Field effect transistors; Heterojunction semiconductor devices; EPITAXY; PLANARIZATION;

D O I：

10.1016/j.jcrysgro.2008.11.012

中图分类号：

O7 [晶体学];

学科分类号：

0702 ; 070205 ; 0703 ; 080501 ;

摘要：

Advanced III-V transistors require unprecedented low-resistance contacts in order to simultaneously scale bandwidth, f(max) and f(t) with the physical active region [M.J.W. Rodwell, M. Le, B. Brar, in: Proceedings of the IEEE, 96, 2008, p. 748]. Low-resistance contacts have been previously demonstrated using molecular beam epitaxy (MBE), which provides active doping above 4 x 10(19) cm(-3) and permits insitu metal deposition for the lowest resistances [U. Singisetti, M.A. Wistey, J.D. Zimmerman, B.J.Thibeault, M.J.W. Rodwell, A.C. Gossard, S.R. Bank, Appl. Phys. Lett., submitted]. But MBE is a blanket deposition technique, and applying MBE regrowth to deep-submicron lateral device dimensions is difficult even with advanced lithography techniques. We present a simple method for selectively etching undesired regrowth from the gate or mesa of a III-V MOSFET or laser, resulting in self-aligned source/drain contacts regardless of the device dimensions. This turns MBE into an effectively selective area growth technique. (C) 2008 Elsevier B.V. All rights reserved.

引用

页码：1984 / 1987

页数：4

共 12 条

[1] Self-aligning planarization and passivation for integration applications in III-V semiconductor devices [J].