A 12 Gb/s Standard Cell Based ECL 4:1 Serializer with Asynchronous Parallel Interface

被引：0

作者：

Schrape, Oliver ^{[1
]}

Appel, Markus ^{[2
]}

Winkler, Frank ^{[2
]}

Krstic, Milos ^{[1
]}

机构：

[1] IHP, Technol Pk 25, D-15236 Frankfurt, Oder, Germany

[2] Humboldt Univ, Berlin 10099, Germany

来源：

2013 IEEE 20TH INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS (ICECS) | 2013年

关键词：

Serializer; Emitter Coupled Logic; ECL; CML; Micropipelines; SerDes; MUX;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an implementation of an high speed, double data rate, fully differential ECL (Emitter Coupled Logic) serializer. For this purpose, a novel robust ECL standard cell library was developed. The design is composed using a digital design flow, described in Hardware Description Language (HDL), and transfered manually in the analog design environment. The serializer has a parallel 4-bit FIFO interface, and can either communicate synchronously or asynchronously using the 2-phase bundled-data protocol. The FIFO consists of 4 stages and is realized as a micropipeline with a Muller pipeline as backbone. The entire circuit is developed in a 0.25 mu m SiGe BiCMOS process and operates nominally at 3.3V. Simulation results show a maximal data rate of 12 Gb/s while drawing a current of 96.64 mA only. Finally, the design and its components are compared to other SiGe-based published implementations.

引用

页码：1 / 4

页数：4