A Programmable Controller Architecture for Regular Expression String Matching

The expressive power of regular expressions has been often adopted in network intrusion detection systems, virus scanners, and spam filtering applications. However in the CPU based systems, pattern matching is one of the most computation intensive parts. In this paper, we present the design, implementation and evaluation of a regular expression string matching programmable controller (SMPC). This special purpose controller is a parallel and pipelined processor architecture which can deal with the regular expression semantics. Two hardware stacks are implemented in SMPC to support fast branches when the non-matching occurs. Our implementation processes 4 characters per clock cycle (maximum performance of state of the art solutions) and occupies only O(n) memory (where n is the length of the regular expression). Via synthesizing the verilog description and analyzing area/time constraints, SMPC can achieve 200 similar to 400 times speedup over traditional CPU implementations and up to 7.9Gbps in processing throughput. Besides it outperforms the counterparts greatly as the complexity of regular expressions increases.