LDTFI: Layout-aware Timing Fault-Injection Attack Assessment Against Differential Fault Analysis

Attackers can target a cryptographic hardware design with a low-cost setup and little effort to inject timing faults, which can be exploited to leak secret keys when paired with differential fault analysis (DFA). In the literature, proposed analysis methods and countermeasures against such attacks target higher design abstractions (e.g., RTL and gate level), and incur large area and latency overhead. Moreover, none of these proposed methodologies account for timing variations incurred by design during layout generation. In this paper, we propose an LDTFI framework to automatically analyze the viability of clock-glitch-based timing faults to perform DFA and then apply countermeasures at the layout level. LDTFI first assesses the feasibility of injecting controlled timing faults into crypto designs needed for successful DFA and then provides its vulnerability. After that, to render DFA ineffective, we ingeniously modify the design's layout to alter the path delays of security-critical registers. In contrast to system-wide countermeasures, we administer countermeasures locally to security-critical paths. As a result, these countermeasures incur minimal area and no latency overhead to the design. The framework's efficacy is shown by accounting for the DFA attack on the pipelined implementation of an AES design.