A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration

This paper explores a new topology of charge-pump PLL intended for.S-fractional-N frequency synthesis. Thanks to the adoption of a bang-bang phase detector and a two-path analog loop filter, the impact of charge-pump noise on PLL phase noise is reduced to negligible levels with no penalty on power dissipation. Additionally, the proposed topology enables an efficient cancellation of the Delta Sigma quantization error, a novel scheme for the calibration of the loop filter parameters and a low-sensitivity VCO, which is beneficial in lowering the reference-spur level. The 3.0-to-4.0-GHz fractional-N synthesizer integrated in a 65-nm CMOS technology consumes 5 mW from a 1.2-V voltage supply. The flat phase noise is -105 dBc/Hz over the 5.5-MHz PLL bandwidth with a 40-MHz crystal reference.