Transient Electrothermal Analysis of Multilevel Interconnects in the Presence of ESD Pulses Using the Nonlinear Time-Domain Finite-Element Method

被引:36
作者
Shi, Yan-Bing [1 ]
Yin, Wen-Yan [1 ]
Mao, Jun-Fa [1 ]
Liu, Peiguo [2 ]
Liu, Qing Huo [3 ]
机构
[1] Shanghai Jiao Tong Univ, Sch Elect Informat & Elect Engn, Ctr Microwave & RF Technol, Shanghai 200240, Peoples R China
[2] Natl Univ Def Technol, Dept Elect Sci & Engn, Changsha, Hunan, Peoples R China
[3] Duke Univ, Dept Elect & Comp Engn, Durham, NC USA
关键词
Electrostatic discharges (ESDs); electrothermal effects; finite-element method (FEM); interconnects; time-domain analysis; THERMAL SIMULATION; FAILURE; POLYIMIDE;
D O I
10.1109/TEMC.2009.2017026
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Comprehensive electrothermal analysis of multilevel interconnects under electrostatic discharge (ESD) stress is carried out using the proposed nonlinear time-domain finite-element method (FEM). The technological, structural, and material parameters used in the analysis correspond to the advanced CMOS process of 90-, 65-, 45, and 32-nm nodes assessed by the International Technology Roadmap for Semiconductors. In order to enhance the computation efficiency and to reduce the memory cost, the preconditioned conjugated gradient technique combined with the element-by-element approximate factorization method is introduced to handle the sparsematrices formed by FEM. The nonlinear material parameters including the temperature-dependent electrical and thermal conductivities are treated rigorously. The transient temperature distributions, the maximum temperatures, and the temperature rise time of 3- and 4-level interconnect structures under the injection of ESD pulses with various waveforms are obtained and discussed.
引用
收藏
页码:774 / 783
页数:10
相关论文
共 30 条
[1]   Modelling of thermal failure of metallic interconnects under electrostatic discharge transients [J].
Amin, KM ;
Fikry, W ;
Sabry, MN ;
Ragai, HF .
ELECTRONICS LETTERS, 2005, 41 (19) :1056-1057
[2]   High-current failure model for VLSI interconnects under short-pulse stress conditions [J].
Banerjee, K ;
Amerasekera, A ;
Cheung, N ;
Hu, CM .
IEEE ELECTRON DEVICE LETTERS, 1997, 18 (09) :405-407
[3]   Global (interconnect) warming [J].
Banerjee, K ;
Mehrotra, A .
IEEE CIRCUITS & DEVICES, 2001, 17 (05) :16-32
[4]   Compact modeling and SPICE-based simulation for electrothermal analysis of multilevel ULSI interconnects [J].
Chiang, TY ;
Banerjee, K ;
Saraswat, KC .
ICCAD 2001: IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, 2001, :165-172
[5]   Multiple-time-instant 2D thermal mapping during a single ESD event [J].
Dubec, V ;
Bychikhin, S ;
Blaho, A ;
Heer, M ;
Pogany, D ;
Denison, M ;
Jensen, N ;
Stecher, M ;
Groos, G ;
Gornik, E .
MICROELECTRONICS RELIABILITY, 2004, 44 (9-11) :1793-1798
[6]  
GOLIO M, 2001, RF MICROWAVE HDB, pA8
[7]   USE OF THE 3-DIMENSIONAL TLM METHOD IN THE THERMAL SIMULATION AND DESIGN OF SEMICONDUCTOR-DEVICES [J].
GUI, X ;
WEBB, PW ;
GAO, GB .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1992, 39 (06) :1295-1302
[8]   THERMAL SIMULATION OF THIN-FILM INTERCONNECT FAILURE CAUSED BY HIGH-CURRENT PULSES [J].
GUI, X ;
DEW, SK ;
BRETT, MJ .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1995, 42 (07) :1386-1388
[9]   Dynamic temperature rise of shielded MR sensors during simulated electrostatic discharge pulses of variable pulse width [J].
Iben, IET .
JOURNAL OF ELECTROSTATICS, 2006, 64 (02) :151-163
[10]   Scaling analysis of multilevel interconnect temperatures for high-performance ICs [J].
Im, S ;
Srivastava, N ;
Banerjee, K ;
Goodson, KE .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2005, 52 (12) :2710-2719