Energy-efficient switching scheme for SAR ADCs using two reference levels

被引：2

作者：

Li, Junhui ^{[1
]}

Huang, Linlin ^{[1
]}

Zhang, Lizhen ^{[1
]}

Li, Xin ^{[1
]}

Wu, Jianhui ^{[1
,2
]}

机构：

[1] Southeast Univ, Natl ASIC Res Ctr, Nanjing 210096, Jiangsu, Peoples R China

[2] Southeast Univ, Jiangsu Prov Key Lab Sensor Network Technol, Nanjing 210096, Jiangsu, Peoples R China

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2021年 / 106卷 / 03期

基金：

中国国家自然科学基金;

关键词：

SAR ADC; Switching scheme; Merge-and-split; Reference level; Switching energy; REDUCTION;

D O I：

10.1007/s10470-020-01787-7

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A highly energy-efficient capacitor switching scheme for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. The proposed switching scheme needs only two reference levels by using the merge-and-split technique, which eliminates the need of the extra reference voltage (V-cm). The switching procedure is performed on the simple binary weighted capacitor arrays without any capacitor-splitting. Compared with the conventional scheme, the proposed switching scheme can achieve 98.45% saving in switching energy and 75% capacitors-area reduction. Besides, because two capacitor arrays are switched symmetrically, the common-mode voltage of capacitive digital-to-analog converter (CDAC) keeps constant until the LSB cycle. The proposed switching scheme is verified in a 0.6-V 10-bit 200-kS/s SAR ADC in 40 nm CMOS technology.

引用

页码：661 / 667

页数：7

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