High soft-error tolerance body-tied SOI technology with partial trench isolation (PTI) for next generation devices

被引：9

作者：

Hirano, Y ^{[1
]}

Iwamatsu, T ^{[1
]}

Shiga, K ^{[1
]}

Nii, K ^{[1
]}

Sonoda, K ^{[1
]}

Matsumoto, T ^{[1
]}

Maeda, S ^{[1
]}

Yamaguchi, Y ^{[1
]}

Ipposhi, T ^{[1
]}

Maegawa, S ^{[1
]}

Inoue, Y ^{[1
]}

机构：

[1] Mitsubishi Electr Corp, ULSI Dev Ctr, Itami, Hyogo 6648641, Japan

来源：

2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2002年

关键词：

D O I：

10.1109/VLSIT.2002.1015383

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

It was proven that the body-tied SOI technology with partial trench isolation (PTI) has significant high soft-error immunity. As compared with the bulk, a three-order reduction of the soft-error rate for a 0.18mum SOI 4M-bit SRAM with the PTI was successfully realized by the balanced combination of the SOI thickness and well resistance. It is estimated that the soft-error immunity for the floating-body device degrades because large charge collection is induced by not only the body strike but also the drain strike. A design guideline of the SOI structure to suppress soft errors is presented. According to the guideline, beyond 0.13mum node, high soft-error immunity for the body-tied SOI device was projected as compared with the bulk as well as the body-floating SOI device.

引用

页码：48 / 49

页数：2

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