Design of low-power clock generator synchronized with AC power for adiabatic dynamic CMOS logic

被引：4
|
作者：
Cho, Seung-Il [1 ]
Kim, Seong-Kweon [2 ]
Harada, Tomochika [1 ]
Yokoyama, Michio [1 ]
机构：
[1] Yamagata Univ, Grad Sch Sci & Engn, Yonezawa, Yamagata 9928510, Japan
[2] Seoul Natl Univ Sci & Technol, Dept Elect & IT Media Engn, Seoul 139743, South Korea
来源：
IEICE ELECTRONICS EXPRESS | 2013年 / 10卷 / 20期
关键词：
synchronization; low-power clock generator; adiabatic dynamic CMOS logic (ADCL); wave shaping circuit (WSC); asymmetry duty ratio divider (ADD); ULTRA-LOW-POWER;
D O I：
10.1587/elex.10.20130716
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
To reduce the power dissipation in conventional CMOS logic and to maintain adiabatic charging and discharging with low power for the adiabatic dynamic CMOS logic (ADCL), the clock signal of logic circuits should be synchronized with the AC power source. In this paper, the low-power clock generator synchronized with the AC power signal is proposed for ADCL system. From the simulation result, summation of power consumption of the designed wave shaping circuit (WSC) and asymmetry duty ratio divider (ADD) was estimated with approximately 1.197 mu W and 58.1 mu W at 3 kHz and 10 MHz, respectively.
引用
收藏
页数：9
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