Evaluating the impact of resistance in carbon nanotube bundles for VLSI interconnect using diameter-dependent modeling techniques

Single-walled carbon nanotube (SWCNT) bundles have the potential to provide an attractive solution for the resistivity and electromigration problems faced by traditional copper interconnects. This paper discusses the modeling of nanotube bundle resistance for on-chip interconnect applications. Based on recent experimental results, the authors model the impact of nanotube diameter on contact and ohmic resistance, which has been largely ignored in previous bundle models. The results indicate that neglecting the diameter-dependent nature of ohmic and contact resistances can produce significant errors. Using the resistance model, it is shown that SWCNT bundles can provide up to one order of magnitude reduction in resistance when, compared with traditional copper interconnects depending on bundle geometry and individual nanotube diameter. Furthermore, for local interconnect applications, an optimum nanotube diameter exists to minimize the resistance of the carbon nanotube bundle.