共 47 条
[32]
Scaling 2-Layer RRAM Cross-Point Array towards 10 nm Node: a Device-Circuit Co-Design
[J].
2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS),
2015,
:193-196
[33]
A Novel GaN Gate Driver: Transistor-Intrinsic Integration Exploiting Non-Ideal Characteristics by Device-Circuit Co-Design
[J].
2024 36TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND IC S, ISPSD 2024,
2024,
:279-282
[34]
VARIATION-AWARE ENERGY-DELAY OPTIMIZATION METHOD FOR DEVICE/CIRCUIT CO-DESIGN
[J].
2015 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE,
2015,
[35]
Gate-All-Around FET Based 6T SRAM Design Using a Device-Circuit Co-Optimization Framework
[J].
2017 IEEE 60TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS),
2017,
:1113-1116
[36]
A Unified Approach for Trap-Aware Device/Circuit Co-Design in Nanoscale CMOS Technology
[J].
2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM),
2013,
[37]
Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors
[J].
2016 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI),
2016,
:649-654
[40]
Spacer Engineered Junction-less Transistor: A Device Circuit Co-Design Study for Ultra-Low Power Applications
[J].
PROCEEDINGS OF THE 2018 SECOND INTERNATIONAL CONFERENCE ON INTELLIGENT COMPUTING AND CONTROL SYSTEMS (ICICCS),
2018,
:1445-1450