A new area-efficient BCD-digit multiplier

被引：9

作者：

Castillo, Encarnacion ^{[1
]}

Lloris, Antonio ^{[1
]}

Morales, Diego P. ^{[1
]}

Parrilla, Luis ^{[1
]}

Garcia, Antonio ^{[1
]}

Botella, Guillermo ^{[2
]}

机构：

[1] Univ Granada, Dept Elect & Comp Technol, Campus Univ Fuentenueva, Granada 18071, Spain

[2] Univ Complutense Madrid, Dept Comp Architecture & Automat, Madrid 28040, Spain

来源：

DIGITAL SIGNAL PROCESSING | 2017年 / 62卷

关键词：

BOD enconding; Computer arithmetic; FPGA; IoT; Multiplier; DECIMAL MULTIPLICATION; ARCHITECTURE;

D O I：

10.1016/j.dsp.2016.10.011

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In the Internet of Things era, with millions of devices performing financial and commercial operations, decimal arithmetic has become very popular in the computation of many business and commercial applications, in order to maintain decimal rounding and precision. This paper proposes the design and implementation of a new algorithm for decimal multiplication oriented to area reduction. This algorithm is especially suitable for field programmable gate arrays (FPGA) and has thus been implemented on this kind of devices. Results show that the proposed BCD multiplication leads to a significant area reduction without decreasing system performance. (C) 2016 Elsevier Inc. All rights reserved.

引用

页码：1 / 10

页数：10

共 32 条

[1]

Al-Khaleel O.D., 2012, P 8 INT S MECH ITS A, P1

[2]

Al-Khaleel O, 2011, 2011 IEEE 29TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), P226, DOI 10.1109/ICCD.2011.6081401

[3]

[Anonymous], 2019, IEEE std 754-2019 (revision of IEEE 754-2008), P1, DOI [DOI 10.1109/IEEESTD.2019.8766229, 10.1109/IEEESTD.2019.8766229, 10.1109/IEEESTD.2008.4610935, DOI 10.1109/IEEESTD.2008.4610935]

[4]

[Anonymous], 2008, IET POWER ENERGY SER

[5] Pipe lined architecture for real-time cost-optimized extraction of visual primitives based on FPGAs [J].

Barranco, F. ;

Tomasi, M. ;

Diaz, J. ;

Vanegas, M. ;

Ros, E. .

DIGITAL SIGNAL PROCESSING, 2013, 23 (02) :675-688

[6]

Bhattacharya J, 2010, 2010 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AUTOMATION AND TEST (VLSI-DAT), P315, DOI 10.1109/VDAT.2010.5496752

[7] Quantization analysis and enhancement of a VLSI gradient-based motion estimation architecture [J].

Botella, Guillermo ;

Meyer-Baese, Uwe ;

Garcia, Antonio ;

Rodriguez, Manuel .

DIGITAL SIGNAL PROCESSING, 2012, 22 (06) :1174-1187

[8]

Castillo E., 2016, MICROPROCESS MICROSY

[9]

Deschamps Jean-Pierre, 2010, Proceedings of the VI Southern Programmable Logic Conference (SPL), P67, DOI 10.1109/SPL.2010.5483000

[10]

Dlodlo N., 2015, RES TRENDS EXISTING, P539

← 1 2 3 4 →