HW/SW Co-Design and Co-Optimizations for Deep Learning

被引:1
作者
Marchisio, Alberto [1 ]
Putra, Rachmad Vidya Wicaksana [1 ]
Hanif, Muhammad Abdullah [1 ]
Shafique, Muhammad [1 ]
机构
[1] Vienna Univ Technol TU Wien, Vienna, Austria
来源
WORKSHOP PROCEEDINGS 2018: INTELLIGENT EMBEDDED SYSTEMS ARCHITECTURES AND APPLICATIONS (INTESA) | 2018年
关键词
Pruning; Quantization; Deep Learning; Systolic Array;
D O I
10.1145/3285017.3285022
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Deep Learning algorithms have been proven to provide state-of-the-art results in many applications but at the cost of a high computational complexity. Therefore, accelerating such algorithms in hardware is highly needed. However, since the computational requirements are growing exponentially along with the accuracy, their demand for hardware resources is significant. To tackle this issue, we propose a methodology, involving both software and hardware, to optimize the Deep Neural Networks (DNNs). We discuss and analyze pruning, approximations through quantization and specialized accelerators for DNN inference. For each phase of the methodology, we provide quantitative comparisons with the existing techniques and hardware platforms.
引用
收藏
页码:13 / 18
页数:6
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