Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm

被引：161

作者：

Bartenstein, T ^{[1
]}

Heaberlin, D ^{[1
]}

Huisman, L ^{[1
]}

Silwinski, D ^{[1
]}

机构：

[1] IBM Corp, Microelect Div, Armonk, NY 10504 USA

来源：

INTERNATIONAL TEST CONFERENCE 2001, PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/TEST.2001.966644

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new way of diagnosing ICs that fail logic tests will be described. It can handle bridging fault, opens, transition faults and many more complex defects as easily and as accurately as regular stuck-at faults.

引用

页码：287 / 296

页数：10

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