A 2.3-3.9 GHz Fractional-N Frequency Synthesizer with Charge Pump and TDC Calibration for Reduced Reference and Fractional Spurs

被引：4

作者：

Jiang, Junning ^{[1
]}

Yan, Tanwei ^{[1
]}

Zhou, Dadian ^{[1
]}

Karsilayan, Aydin Ilker ^{[1
]}

Silva-Martinez, Jose ^{[1
]}

机构：

[1] Texas A&M Univ, College Stn, TX 77843 USA

来源：

2021 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC) | 2021年

关键词：

5G mobile communication; phase locked loop; charge pump calibration; TDC; DTC; static phase error; spur reduction;

D O I：

10.1109/RFIC51843.2021.9490444

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 2.3-3.9 GHz fractional-N phase locked loop (PLL) with charge pump and a time-to-digital converter (TDC) based calibration for reference and fractional spurs reduction suitable for frequency synthesizers used in 5G mobile communication systems is introduced in this paper. The charge pump PLL includes a digital phase processor composed by a TDC, digital filters and a DTC and it is used for monitoring, tracking, and filtering both reference and fractional spurs simultaneously. Calibrated sub-ranging TDCs and DTC with 1 ps resolution are employed. A non-invasive master-slave calibration methodology is applied to TDCs and DTC with Vernier delay line structure to achieve the required INL and DNL performances. Fabricated in a mainstream 40-nm technology, the PLL is characterized, showing a reference spur level of -108.3 dBc and a fractional spur under -95.0 dBc. The frequency synthesizer's total power consumption when operating at 3.3 GHz is 15.7 mW.

引用

页码：71 / 74

页数：4

共 8 条

[1] Design and analysis of an ultrahigh-speed glitch-free fully differential charge pump with minimum output current variation and accurate matching [J].