Adaptive timing correction technique for pulse-amplitude and pulse-position modulation interface

A timing correction approach is proposed in this article to improve the performance of high-speed serial data link involving pulse position modulation (PPM) and pulse amplitude modulation (PAM) techniques. The proposed technique corrects the timing error that arises from combining the PAM approach with the PPM approach, which allows transmitting more bits and hence achieving higher data rate for the designed serial link. The proposed technique uses the recovered AM bits to adapt the reference voltage of the comparator circuit at the receiver side in order to correct the jitter results from combining the time modulation with the amplitude modulation. A 5-bit 4-Gb/s serial data link that involves PAM and PPM has been designed and simulated using the proposed technique in 130 nm CMOS technology using 800 MHz as an input clock signal. The simulation results indicate that when combining AM and PPM techniques, the total number of the transmitted bits can be increased using the proposed technique. The total power consumption of the proposed link is less than 84 mW. A performance comparison between the proposed link and other serial links has been carried out that indicates an improved performance for serial links involving the proposed technique.