A Novel Energy Efficient High-Speed 10-Transistor Full Adder Cell Based on Pass Transistor Logic

In this paper a new design of 10-T one bit full adder based on Pass Transistor Logic has been proposed with an improved performance in terms of area utilization, power dissipation, and delay characteristics. All the simulations are performed on 70 nm technology node using Tanner EDA tool with supply voltage of 0.9 V. The proposed 10-T Full Adder circuit has average improvement of 68.45%, 68.45%, 89.44%, 66.3% and 66.29% in leakage current, static power, static energy, Dynamic PDP and dynamic EDP respectively as compared to SERF 10-T full adder circuit. Proposed circuit has also improvement in speed by 66.55% as compared to SERF 10T full adder circuit with 25% less area requirement.