Improve Signal Integrity Performance by Using Hybrid PCB Stackup

被引：0

作者：

Mendez Ruiz, Cesar ^{[1
]}

Ye, Chunfei ^{[2
]}

Ye, Xiaoning ^{[2
]}

Lopez, Enrique ^{[1
]}

Yin, Maoxin ^{[3
]}

Hsu, Jimmy ^{[4
]}

Su, Thonas ^{[4
]}

机构：

[1] Intel Tecnol Mexico SA CV, Perifer Sur 7980 Edif 4-E, Tlaquepaque 45600, Jalisco, Mexico

[2] Intel Corp, DCSG, Dupont, WA 98327 USA

[3] Intel Asia Pacific Res & Dev Ltd, DCSG, Shanghai, Peoples R China

[4] Intel Asia Pacific Res & Dev Ltd, DCSG, Taipei 10595, Taiwan

来源：

2013 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC) | 2013年

关键词：

printed circuit board; low loss material; SATA; PCIE; high speed signaling; signal integrity;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

FR4 is a commonly used material in industry to build printed circuit boards. However signals propagating in this media have significant attenuation when date rate gets higher and higher, gating the solution space. Low loss materials can be considered to enable longer board routing but they are very costly for most of commercial platforms. In this paper, hybrid PCB stackup is investigated. The investigation focuses on full channel signal integrity analysis. Simulations for SATA3 and PCIE3 show noticeable improvement of using this hybrid stackup. Such a hybrid is normally less costly than all low loss PCB stackup, thus achieving a good compromising between cost and performance for PCB design and manufacturing.

引用

页码：317 / 321

页数：5

共 8 条

[1] Hall S. H., 2009, Advanced Signal Integrity for High-Speed Digital Designs, V1st, DOI [10.1002/9780470423899, DOI 10.1002/9780470423899]
[2] Huray P. G., 2007, IEEE
[3] Huray P.G., DesignCon 2010
[4] Lu D., 2009, MAT ADV PACKAGING
[5] Wu K. B., 2012, HYBRID STACK UP PRIN
[6] Ye C., IEEE EPEPS 2010, P281
[7] Ye CF, 2011, IEEE INT SYMP ELEC, P803, DOI 10.1109/ISEMC.2011.6038418
[8] Zhang JM, 2012, IEEE INT SYMP ELEC, P554, DOI 10.1109/ISEMC.2012.6351671

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